The minimum dimension that a given photolithography process can resolve is alternatively called the minimum feature-size or the critical dimension. The feature-size is a very important parameter, as reductions in the feature-size tend to improve speed performance of the IC. The feature-size of a printed IC device is not uniform. The printing process results in slight variation of the feature-size from lot-to-lot, from wafer-to wafer, and from device to device within each wafer.
In a circuit, the total electrical current supplied to the collectors of a transistor is referred to as Icc current. As the critical dimensions of transistors are scaled downward, higher density and faster speed requirements result in higher Icc standby currents, especially at higher temperatures. To better predict transistor targets, it is beneficial to know the characteristics of a specific transistor's operation at higher temperature. For Icc standby current, the current method of estimating leakage comprises measuring Icc values at a high temperature, typically 85° C., and at room temperature, 25° C., to create an Icc current temperature scaling factor (ITSF) based on the XY slopes of the fitting curves. From this ITSF, leakages at high temperatures from different wafers and lots with different transistor characteristics can be estimated.
However, this method does not provide an accurate estimation of the ITSF as these fitting curves have different origins on XY plot. Further, measuring Icc current at high temperatures can be time consuming and very costly. Sometimes, the Icc current at a high temperature can be so high that it exceeds the tester measurement limits.
Due to the difficulty of performing Icc measurements at high temperatures and the accuracy limitations of current methods of estimation, it is desirable to accurately estimate Icc currents at various temperatures based on measurements that can be performed at room temperature during wafer sort testing.